Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

Keyphrases

• Spin-transfer Torque Magnetic RAM (STT-MRAM) 100%
• Read Reliability 100%
• Fault Aware 100%
• Error Correction Codes 71%
• Area Cost 14%
• CMOS Technology 14%
• Error Correction 14%
• 64-bit 14%
• Failure Rate 14%
• 40nm CMOS 14%
• Reliability Enhancement 14%
• Concurrent Error Detection 14%
• Enhancement Techniques 14%
• Read Disturb 14%
• Scrubbing 14%
• Scaling Challenges 14%
• Reading Failure 14%

Engineering

• Error Correction 100%
• Correction Code 83%
• Random Access Memory 66%
• Spin Transfer 66%
• Failure Rate 16%
• Bit Word 16%
• Concurrent Error Detection 16%
• Read Disturb 16%
• Washing 16%

Computer Science

• Error Correction Code 100%
• Random Access Memory 80%
• Error Correction 20%
• Concurrent Error Detection 20%