Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

Meng Shan Wu; Yen Lin Chua; Jin Fu Li; Yun Ting Chuan; Shih Hsu Huang

doi:10.1109/ITC-Asia58802.2023.10301173

Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

Meng Shan Wu, Yen Lin Chua, Jin Fu Li, Yun Ting Chuan, Shih Hsu Huang

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

Spin-transfer-torque magnetic random access memory (STT-MRAM) has been considered as a candidate for next-generation memory to cope with the scaling challenges of conventional memories. However, the STT-MRAM has the problem of high read failure rate. Effective reliability-enhancement techniques thus are needed for STT-MRAMs. In this paper, we propose a fault-aware error-correction-code (FA-ECC) scheme for STT-MRAMs. The FA-ECC scheme can distinguish a read disturb fault (RDF) from an incorrect read fault (IRF) such that the IRF can be recovered by adjusting the reference resistance to avoid the effect of fault accumulation. Thus, the FA-ECC scheme can be used for concurrent error detection and correction or scrubbing. Analysis results show that the area cost of the FA-ECC scheme is only about 1711μm² using TSMC 40nm CMOS technology for a STT-MRAM with 64-bit words. Also, the FA-ECC scheme can significantly improve the reliability of STT-MRAM in comparison with a conventional ECC scheme.

原文	???core.languages.en_GB???
主出版物標題	Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9798350312812
DOIs	https://doi.org/10.1109/ITC-Asia58802.2023.10301173
出版狀態	已出版 - 2023
事件	7th IEEE International Test Conference in Asia, ITC-Asia 2023 - Matsue, Japan 持續時間: 13 9月 2023 → 15 9月 2023

出版系列

名字	Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	7th IEEE International Test Conference in Asia, ITC-Asia 2023
國家/地區	Japan
城市	Matsue
期間	13/09/23 → 15/09/23

存取文件

10.1109/ITC-Asia58802.2023.10301173

運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一：運算記憶體之測試策略與自動化技術(3/3)
Li, J.-F. (PI)
1/08/25 → 31/07/26
研究計畫: Research

引用此

Wu, M. S., Chua, Y. L., Li, J. F., Chuan, Y. T., & Huang, S. H. (2023). Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. 於 Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 (Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-Asia58802.2023.10301173

@inproceedings{fe92dfdebca445b0a13e9fe825ba76d0,

title = "Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs",

abstract = "Spin-transfer-torque magnetic random access memory (STT-MRAM) has been considered as a candidate for next-generation memory to cope with the scaling challenges of conventional memories. However, the STT-MRAM has the problem of high read failure rate. Effective reliability-enhancement techniques thus are needed for STT-MRAMs. In this paper, we propose a fault-aware error-correction-code (FA-ECC) scheme for STT-MRAMs. The FA-ECC scheme can distinguish a read disturb fault (RDF) from an incorrect read fault (IRF) such that the IRF can be recovered by adjusting the reference resistance to avoid the effect of fault accumulation. Thus, the FA-ECC scheme can be used for concurrent error detection and correction or scrubbing. Analysis results show that the area cost of the FA-ECC scheme is only about 1711μm2 using TSMC 40nm CMOS technology for a STT-MRAM with 64-bit words. Also, the FA-ECC scheme can significantly improve the reliability of STT-MRAM in comparison with a conventional ECC scheme.",

keywords = "Error Correction Code, STT-MRAM, fault analysis, fault aware, reliability",

author = "Wu, {Meng Shan} and Chua, {Yen Lin} and Li, {Jin Fu} and Chuan, {Yun Ting} and Huang, {Shih Hsu}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 7th IEEE International Test Conference in Asia, ITC-Asia 2023 ; Conference date: 13-09-2023 Through 15-09-2023",

year = "2023",

doi = "10.1109/ITC-Asia58802.2023.10301173",

language = "???core.languages.en_GB???",

series = "Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023",

}

Wu, MS, Chua, YL, Li, JF, Chuan, YT & Huang, SH 2023, Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. 於 Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023. Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023, Institute of Electrical and Electronics Engineers Inc., 7th IEEE International Test Conference in Asia, ITC-Asia 2023, Matsue, Japan, 13/09/23. https://doi.org/10.1109/ITC-Asia58802.2023.10301173

Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. / Wu, Meng Shan; Chua, Yen Lin; Li, Jin Fu 等.
Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

TY - GEN

T1 - Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

AU - Wu, Meng Shan

AU - Chua, Yen Lin

AU - Li, Jin Fu

AU - Chuan, Yun Ting

AU - Huang, Shih Hsu

PY - 2023

Y1 - 2023

N2 - Spin-transfer-torque magnetic random access memory (STT-MRAM) has been considered as a candidate for next-generation memory to cope with the scaling challenges of conventional memories. However, the STT-MRAM has the problem of high read failure rate. Effective reliability-enhancement techniques thus are needed for STT-MRAMs. In this paper, we propose a fault-aware error-correction-code (FA-ECC) scheme for STT-MRAMs. The FA-ECC scheme can distinguish a read disturb fault (RDF) from an incorrect read fault (IRF) such that the IRF can be recovered by adjusting the reference resistance to avoid the effect of fault accumulation. Thus, the FA-ECC scheme can be used for concurrent error detection and correction or scrubbing. Analysis results show that the area cost of the FA-ECC scheme is only about 1711μm2 using TSMC 40nm CMOS technology for a STT-MRAM with 64-bit words. Also, the FA-ECC scheme can significantly improve the reliability of STT-MRAM in comparison with a conventional ECC scheme.

AB - Spin-transfer-torque magnetic random access memory (STT-MRAM) has been considered as a candidate for next-generation memory to cope with the scaling challenges of conventional memories. However, the STT-MRAM has the problem of high read failure rate. Effective reliability-enhancement techniques thus are needed for STT-MRAMs. In this paper, we propose a fault-aware error-correction-code (FA-ECC) scheme for STT-MRAMs. The FA-ECC scheme can distinguish a read disturb fault (RDF) from an incorrect read fault (IRF) such that the IRF can be recovered by adjusting the reference resistance to avoid the effect of fault accumulation. Thus, the FA-ECC scheme can be used for concurrent error detection and correction or scrubbing. Analysis results show that the area cost of the FA-ECC scheme is only about 1711μm2 using TSMC 40nm CMOS technology for a STT-MRAM with 64-bit words. Also, the FA-ECC scheme can significantly improve the reliability of STT-MRAM in comparison with a conventional ECC scheme.

KW - Error Correction Code

KW - STT-MRAM

KW - fault analysis

KW - fault aware

KW - reliability

UR - http://www.scopus.com/inward/record.url?scp=85178622975&partnerID=8YFLogxK

U2 - 10.1109/ITC-Asia58802.2023.10301173

DO - 10.1109/ITC-Asia58802.2023.10301173

M3 - 會議論文篇章

AN - SCOPUS:85178622975

T3 - Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023

BT - Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 7th IEEE International Test Conference in Asia, ITC-Asia 2023

Y2 - 13 September 2023 through 15 September 2023

ER -

Wu MS, Chua YL, Li JF, Chuan YT, Huang SH. Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. 於 Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023). doi: 10.1109/ITC-Asia58802.2023.10301173

Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

摘要

出版系列

???event.eventtypes.event.conference???

存取文件

指紋

專案

運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一：運算記憶體之測試策略與自動化技術(3/3)

引用此