Fault-Aware Dependability Enhancement Techniques for Flash Memories

Shyue Kung Lu, Shu Chi Yu, Chun Lung Hsu, Chi Tien Sun, Masaki Hashizume, Hiroyuki Yotsuyanagi

研究成果: 雜誌貢獻期刊論文同行評審

1 引文 斯高帕斯(Scopus)

摘要

By analyzing the fault behaviors of conventional flash memory fault models, two new concise fault types are proposed: the 1-safe fault and the 0-safe fault. For a 1(0)-safe fault, if logic 1(0) is programmed into the faulty cell, the effect of the fault can be masked. Data shaping (DS) and the page address remapping (PAR) techniques are used to increase the masking probability. DS manipulates the data patterns so that they can be written into the flash pages safely. PAR scrambles the logical-to-physical address mapping for data words and buffer words. Since the effect of a fault is masked for a large proportion of faulty cells, the burden on the error-correction code (ECC) is reduced, as is the number of incorporated redundancies. A novel test-and-repair flow is proposed that uses DS and PAR and corresponding hardware architectures are also developed. A simulator is used to evaluate the hardware overhead, the repair rate, the yield, and the reliability. The experimental results show that these measures are significantly improved with an almost negligible hardware overhead.

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文章編號8944035
頁(從 - 到)634-645
頁數12
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
28
發行號3
DOIs
出版狀態已出版 - 3月 2020

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