Fanout fault analysis for digital logic circuits

Jwu E. Chen; Chung Len Lee; Wen Zen Shen; Beyin Chen

doi:10.1109/ats.1995.485313

Fanout fault analysis for digital logic circuits

Jwu E. Chen, Chung Len Lee, Wen Zen Shen, Beyin Chen

電機工程學系

研究成果: 雜誌貢獻 › 會議論文 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2approx.8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.

原文	???core.languages.en_GB???
頁（從 - 到）	33-39
頁數	7
期刊	Proceedings of the Asian Test Symposium
DOIs	https://doi.org/10.1109/ats.1995.485313
出版狀態	已出版 - 1995
事件	Proceedings of the 1995 4th Asian Test Symposium - Bangalore, India 持續時間: 23 11月 1995 → 24 11月 1995

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10.1109/ats.1995.485313

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AB - Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2approx.8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.

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Fanout fault analysis for digital logic circuits

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