Evaluation driven layout synthesis

A. C.H. Wu, D. D. Gajski, G. D. Chen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

The authors describe a layout synthesis system for layout generation from generalized register-transfer schematics. This system uses the SLAM partitioner and the ICDB component server. The system is performed in a completely top-down manner which generates the layout by considering the component layout style, floorplan, and critical paths simultaneously. This improves the overall area utilization and minimizes the critical wire lengths, which in turn yields better performance.

原文???core.languages.en_GB???
主出版物標題1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991
發行者Institute of Electrical and Electronics Engineers Inc.
頁面167-171
頁數5
ISBN(電子)078030036X, 9780780300361
DOIs
出版狀態已出版 - 1991
事件1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991 - Taipei, Taiwan
持續時間: 22 5月 199124 5月 1991

出版系列

名字International Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN(列印)1930-8868

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???event.eventtypes.event.conference???1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991
國家/地區Taiwan
城市Taipei
期間22/05/9124/05/91

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