Equivalent Circuit Synthesis of Multiport S Parameters in Pole-Residue Form

Chiu Chih Chou, Jose E. Schutt-Aine

研究成果: 雜誌貢獻期刊論文同行評審

摘要

Equivalent circuit synthesis of an interconnect macromodel is commonly used as an intermediate step before conducting transient simulation of the channel. Depending on the type, for example, $S$ , $Y$ , and $Z$ parameters, and form, for example, pole-residue, state-space, of the macromodel, various circuit topologies have been proposed in the literature. In this article, we focus on the synthesis of multiport $S$ parameters in the pole-residue form. A topology widely used in commercial software is to convert the pole-residue model into a sparse state-space model and then realize the state equations and output equations using capacitors, resistors, and controlled sources. Another topology, based on the generalized pi-model, has also been proposed. In this article, we show that although these conventional methods work well for the multi-input multi-output (MIMO) case (all $S_{ij}$ share a common set of poles), they are not optimal in terms of circuit complexity for the multi- single-input-single-output (SISO) case (each $S_{ij}$ has its own distinct poles). A new topology is proposed accordingly, which has smaller complexity than the conventional ones. Transient simulation on four different circuit solvers is performed to compare the efficiencies of the various topologies. It is found that the proposed topology can achieve more than 1.3 times speedup against the conventional topologies (except the one with explicit pole/residue specification) on most simulators, in terms of the normalized time per step.

原文???core.languages.en_GB???
頁(從 - 到)1971-1979
頁數9
期刊IEEE Transactions on Components, Packaging and Manufacturing Technology
11
發行號11
DOIs
出版狀態已出版 - 1 11月 2021

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