Enhancing the data analysis in IC testing by machine learning techniques

Tsung Han Tsai, Yu Chen Lee, Chi Yu Hsieh

研究成果: 書貢獻/報告類型會議論文篇章同行評審

3 引文 斯高帕斯(Scopus)

摘要

In the IC design process, the test process is the main factor of production cost. Existing tests rely on additional analysis of testing result data by the customer to determine the status of the process. Thus it could take an additional amount of time and cannot make adjustments of the process immediately. In this paper we propose a method to enhance the data analysis in IC testing by machine learning techniques. Our method is based on collecting IC electrical parameters through STDF (Standard Test Data Format) files. The parameters will be transferred to a set of vectors and then classified the errors by SVM classifier and deep learning model.The dataset is consisted of 9 products, seven for training data, one for validation set, and one for test set. Totally 4,337 LOTs are in the dataset. Because each step of the test may cause the problems, the error types include machine error, interface error and site error (8 sites in total). We define 11 categories to classify and 400 LOTs to test the model. Finally, the test accuracy is 86%. With the model, we can find the correlation between the causes of errors and the electrical parameters. After obtaining the electrical parameters of the test, the error cause can be corrected, and the performance function of the monitoring test equipment station can be achieved. As a result it can reduce the time for the customer to analyze the data and make early judgments.During the test process, the program uses deep learning algorithm to get the correlation of the test items and the distribution characteristics of the test results with the small batches of test results of wafers. According to the distribution of test results of electrical properties, the samples with the least difference from other wafers are selected as the excellent products. At the same time, the deep learning model is applied to find highly dependent data in the test results. By reducing these items, the test time could be reduced. The methods above are integrated into the testing process of good, bad and excellent products. It can be used for testing of remaining wafer to reduce the time and the cost required by overall testing.

原文???core.languages.en_GB???
主出版物標題IMPACT 2019 - 14th International Microsystems, Packaging, Assembly and Circuits Technology Conference, Proceeding
發行者IEEE Computer Society
頁面183-186
頁數4
ISBN(電子)9781728160702
DOIs
出版狀態已出版 - 10月 2019
事件14th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2019 - Taipei, Taiwan
持續時間: 23 10月 201925 10月 2019

出版系列

名字Proceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT
2019-October
ISSN(列印)2150-5934
ISSN(電子)2150-5942

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???event.eventtypes.event.conference???14th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2019
國家/地區Taiwan
城市Taipei
期間23/10/1925/10/19

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