Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS2FETs for SoC Scaling

Vita Pi Ho Hu, Cheng Wei Su, Yen Wei Lee, Tun Yi Ho, Chao Ching Cheng, Tzu Chiang Chen, Terry Yi Tse Hung, Jin Fu Li, Yu Guang Chen, Lain Jong Li

研究成果: 雜誌貢獻期刊論文同行評審

7 引文 斯高帕斯(Scopus)

摘要

In this article, we propose an energy-efficient monolithic 3-D (M3D) three-Tier SRAM cell with back-end-of-The-line (BEOL) back-gated (BG) MoS2 FETs. The impacts of wire routing resistance and capacitance, gate topology of MoS2 FETs, and the layout optimization of multitier 6T SRAM cells have been comprehensively analyzed for SoC scaling through system-Technology co-optimization. SRAM plays an integral role in the performance of SoCs, and the performance can be improved by SRAM on logic integration. Compared with one-Tier BG SRAM cell design, the proposed monolithic three-Tier BG SRAM cell releases the impact of metal line resistance and shows a 44.3% reduction in cell area, 28.4% improvement in read access time, 21.3% improvement in dynamic energy, and 43.6% improvement in energy-delay product. The energy-and area-efficient three-Tier BG SRAM cell enables intelligent functionalities for the area-and energy-constrained edge computing devices.

原文???core.languages.en_GB???
文章編號9184285
頁(從 - 到)4216-4221
頁數6
期刊IEEE Transactions on Electron Devices
67
發行號10
DOIs
出版狀態已出版 - 10月 2020

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