Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory

Tseng Yi Chen, Yuan Hao Chang, Chien Chung Ho, Shuo Han Chen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

24 引文 斯高帕斯(Scopus)

摘要

3D NAND has been proposed to provide a large capacity storage with low-cost consideration due to its high density memory architecture. However, 3D NAND needs to consume enormous time for garbage collection because of live-page copying overhead and long block erase time. To alleviate the impact of live-page copying on the performance of 3D NAND, a sub-block erase design has been designed. With sub-block erase design, this paper proposes a performance booster strategy to extremely boost the performance of garbage collection. As experimental results shows, the proposed strategy has a significant improvement on the average response time.

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主出版物標題Proceedings of the 53rd Annual Design Automation Conference, DAC 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781450342360
DOIs
出版狀態已出版 - 5 6月 2016
事件53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States
持續時間: 5 6月 20169 6月 2016

出版系列

名字Proceedings - Design Automation Conference
05-09-June-2016
ISSN(列印)0738-100X

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???event.eventtypes.event.conference???53rd Annual ACM IEEE Design Automation Conference, DAC 2016
國家/地區United States
城市Austin
期間5/06/169/06/16

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