This paper presents efficient testing methodologies for conditional sum adders. A conditional sum adder consists of conditional cells and selection cells. We propose a design-for-testability (DFT) technique to modify the conditional cells of a conditional sum adder. Then a test scheme is used for detecting the conditional sum adder with single cell fault model (CFM). The proposed test scheme only needs very low test complexity to test a conditional sum adder. For example, the number of test patterns for a 64-bit conditional sum adder is only 9. The ratio of the number of test patterns of the proposed test scheme to the number of the test patterns of the previous scheme  is only about 1%. Also, experimental results show that the area overhead is only about 2.8% for a 64-bit conditioal sum adder with the DFT scheme.
|頁（從 - 到）||319-324|
|期刊||Proceedings of the Asian Test Symposium|
|出版狀態||已出版 - 2004|
|事件||Proceedings of the Asian Test Symposium, ATS'04 - Kenting, Taiwan|
持續時間: 15 11月 2004 → 17 11月 2004