TY - JOUR
T1 - Efficient FFT network testing and diagnosis schemes
AU - Li, Jin Fu
AU - Wu, Cheng Wen
PY - 2002/6
Y1 - 2002/6
N2 - We consider offline testing, design-for-testability, and diagnosis for fast Fourier transform (FFT) networks. A practical FFT chip can contain millions of gates, so effective testing and fault-tolerance techniques usually are required in order to guarantee high-quality products. We propose M-testability conditions for FFT butterfly, omega, and flip networks at the double-multiply-subtract-add (DMSA) module level. A novel design-for-testability technique based on the functional bijectivity property of the specified modules to detect faults other than the cell faults is presented. It guarantees 100% combinational fault coverage with negligible hardware overhead-about 0.17% for an FFT network with 16-bit operand words, independent of the network size. Our design requires fewer test vectors compared with previous ones-a factor of up to 1/(6 × 2 5n), where n is the word length. We also propose C-diagnosability conditions and a C-diagnosable FFT network design. By properly exchanging and blocking certain fault propagation paths, a faulty DMSA module can be located using a two-phase deterministic algorithm. The blocking mechanism can be implemented with no additional hardware. Compared with previous schemes, our design reduces the diagnosis complexity from O(N) to O(1). For both testing and diagnosis, the hardware overhead for our approach is only about 0.43% for 16-bit numbers regardless of the FFT network size.
AB - We consider offline testing, design-for-testability, and diagnosis for fast Fourier transform (FFT) networks. A practical FFT chip can contain millions of gates, so effective testing and fault-tolerance techniques usually are required in order to guarantee high-quality products. We propose M-testability conditions for FFT butterfly, omega, and flip networks at the double-multiply-subtract-add (DMSA) module level. A novel design-for-testability technique based on the functional bijectivity property of the specified modules to detect faults other than the cell faults is presented. It guarantees 100% combinational fault coverage with negligible hardware overhead-about 0.17% for an FFT network with 16-bit operand words, independent of the network size. Our design requires fewer test vectors compared with previous ones-a factor of up to 1/(6 × 2 5n), where n is the word length. We also propose C-diagnosability conditions and a C-diagnosable FFT network design. By properly exchanging and blocking certain fault propagation paths, a faulty DMSA module can be located using a two-phase deterministic algorithm. The blocking mechanism can be implemented with no additional hardware. Compared with previous schemes, our design reduces the diagnosis complexity from O(N) to O(1). For both testing and diagnosis, the hardware overhead for our approach is only about 0.43% for 16-bit numbers regardless of the FFT network size.
KW - Butterfly network
KW - C-testable
KW - Design-for-diagnosability
KW - Design-for-testability
KW - Diagnosis
KW - Fa ult tolerance
KW - Fast Fourier transform (FFT)
KW - Logic testing
KW - M-testable
UR - http://www.scopus.com/inward/record.url?scp=0036625243&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2002.1043329
DO - 10.1109/TVLSI.2002.1043329
M3 - 期刊論文
AN - SCOPUS:0036625243
SN - 1063-8210
VL - 10
SP - 267
EP - 277
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 3
ER -