Efficient block-level connectivity verification algorithms for embedded memories

研究成果: 雜誌貢獻期刊論文同行評審

1 引文 斯高帕斯(Scopus)


A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if multiple memory blocks are integrated into a single system, the STE approach cannot verify it economically. This paper introduces algorithms for verifying block-level connectivity of memories. The verification time of a large memory can be reduced drastically by using bottom-up verification scheme. That is, a memory block is first verified thoroughly, and then only the interconnection between memory blocks of the large memory needs to be verified. The proposed verification algorithms require (3n+2(⌈log 2n⌉+l)+3⌈log2m⌉) Read/Write operations for a 2n×m-bit memory, where n and m are the address width and data width, respectively. Also, the algorithms can verify 100% of the inter-port and intra-port signal misplaced faults of the address, data input, and data output ports.

頁(從 - 到)3185-3192
期刊IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
出版狀態已出版 - 12月 2004


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