During the formation of Ge fin structures on a silicon-on-insulator (SOI) substrate, we found that the dry etching process must be carefully controlled. Otherwise, it may lead to Ge over-etching or the formation of an undesirable Ge fin profile. If the etching process is not well controlled, the top Ge/SOI structure is etched away, and only the Si fin layer remains. In this case, the device exhibits abnormal characteristics. The etching process is emerging as a critical step in device scaling and packaging and affects attempts to increase the packing density and improve device performance. Therefore, it is suggested that optimization of operating the plasma reactor be performed through simulations, in order to not only adjust the process parameters used but also to modify the hardware employed. We are going to develop Ge junction-less devices by employing updated fabrication parameters. Besides, we want to eliminate misfit dislocations at the interface or to reduce threading dislocations by applying cyclic thermal annealing process to meet the goal of obtaining suspended structure of epitaxial Ge layers with high quality.