Double-gate two-step source/drain poly-Si thin-film transistor

Feng Tso Chien, Chih Ping Hung, Hsien Chin Chiu, Tsung Kuei Kang, Ching Hwa Cheng, Yao Tsung Tsai

研究成果: 雜誌貢獻期刊論文同行評審

3 引文 斯高帕斯(Scopus)


A current improved and electric field reduced double-gate (DG) polycrystalline silicon thin-film transistor with two-step source/drain (DGTSD-TFT) design is proposed and demonstrated in this study. The two-step source/drain (TSD) design, which consists of a raised source/drain (RSD) area together with a partial gate overlapped lightly doped drain (P-GOLDD) structure, can lower the device drain electric field (DEF) to reveal a better device performance. Comparisons have been made with respect to a traditional single top gate (STG) device. The operation current of the proposed DGTSD-TFT is almost twice as large as that of the STG structure. The OFF-state leakage current and kink effect, as well as the ON/OFF current ratio for this double-gate and two-step source/drain structure, are also improved simultaneously because of a reduced DEF. A hot carrier stress test reveals that that two-step source/drain structure can achieve more stable device characteristics than the traditional device.

出版狀態已出版 - 4月 2019


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