DOC: A Novel DOuble-Contour-Based Macro Placement Framework for Mixed-Size Designs

Due to the rapid technology scaling and complexity increasing in modern IC designs, a chip often contains thousands of macros and millions of standard cells. In the back-end physical design, the placement becomes a significant challenge in the presence of large number of macros nowadays. To swiftly obtain low-power, high-efficiency, and low-cost chips, design factors such as total wirelength is usually considered as an important matric during placement stage. Conventionally, the position of the macro in initial placement is roughly determined by minimizing the wirelength at prototyping stage. After that, at macro placement stage, the location of each macro is adjusted to form a legal placement solution without increasing total wirelength. Finally, standard cells are placed based on the macro placement result. Among all three stages, the macro placement stage is crucial since the macro placement result will seriously impact the quality of standard cell placement as well as total wirelength. Therefore, in this paper, we propose a novel macro placement framework with the concept of "double contour" to find legal placement result of macros with minimum total wirelength. Specifically, our framework can be divided into two stages, the legal placement stage and optimization stage. In legal placement stage, we apply two contours which macro can be align with so the solution space is increased and the better legal placement result could be obtained. In optimization stage, we propose a simulated annealing based (SA-based) approach to further optimize the result by flipping and fine¬ grained moving macros. Experimental results show that our method can reduce total wirelength up to 12.5% compared with conventional single-contour-based method.