Design verification by using universal test sets

Beyin Chen; Chung Len Lee; Jwu E. Chen

Design verification by using universal test sets

Beyin Chen, Chung Len Lee, Jwu E. Chen

電機工程學系

研究成果: 雜誌貢獻 › 會議論文 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then, theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.

原文	???core.languages.en_GB???
頁（從 - 到）	261-266
頁數	6
期刊	Proceedings of the Asian Test Symposium
出版狀態	已出版 - 1994
事件	Proceedings of the 3rd Asian Test Symposium - Nara, Jpn 持續時間: 15 11月 1994 → 17 11月 1994

引用此

@article{d07762a681604e41a8ac14292b586668,

title = "Design verification by using universal test sets",

abstract = "In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then, theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.",

author = "Beyin Chen and Lee, {Chung Len} and Chen, {Jwu E.}",

year = "1994",

language = "???core.languages.en_GB???",

pages = "261--266",

journal = "Proceedings of the Asian Test Symposium",

issn = "1081-7735",

note = "Proceedings of the 3rd Asian Test Symposium ; Conference date: 15-11-1994 Through 17-11-1994",

}

TY - JOUR

T1 - Design verification by using universal test sets

AU - Chen, Beyin

AU - Lee, Chung Len

AU - Chen, Jwu E.

PY - 1994

Y1 - 1994

N2 - In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then, theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.

AB - In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then, theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.

UR - http://www.scopus.com/inward/record.url?scp=0028713348&partnerID=8YFLogxK

M3 - 會議論文

AN - SCOPUS:0028713348

SN - 1081-7735

SP - 261

EP - 266

JO - Proceedings of the Asian Test Symposium

JF - Proceedings of the Asian Test Symposium

T2 - Proceedings of the 3rd Asian Test Symposium

Y2 - 15 November 1994 through 17 November 1994

ER -

Design verification by using universal test sets

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