Design of reconfigurable carry select adders

Jin Fu Li, Yao Chang Kuo, Chao Da Huang, Tsu Wei Tseng, Chin Long Wey

研究成果: 會議貢獻類型會議論文同行評審

1 引文 斯高帕斯(Scopus)

摘要

Digital signal processing (DSP) processors for real-time processing of multimedia signals usually include fast reconfigurable parallel adders for the operations of integers with different precisions. This paper presents a reconfigurable carry select adder (CSA). High reconfigurability is achieved with inter-block and infra-block partition schemes. This methodology only causes very small performance penalty and area overhead. Experimental results show that the worst delay of a 64-bit reconfigurable CSA with eight 8-bit blocks is about 2.4ns based on the TSMC 0.18μm technology. Also, the area overhead of the additional partition circuitry is only about 4.6%.

原文???core.languages.en_GB???
頁面825-828
頁數4
出版狀態已出版 - 2004
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 6 12月 20049 12月 2004

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???event.eventtypes.event.conference???2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家/地區Taiwan
城市Tainan
期間6/12/049/12/04

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