A reconfigurable structure allows us to provide a large number of resources that can be used in different ways by different applications. This paper presents the design methodology of reconfigurable array multipliers. A 64-bit reconfigurable multiplier can execute one 64-bit, two 32-bit, four 16-bit, and eight 8-bit multiplications depending upon three control signals. The hardware overhead includes 192 two-input AND gates and 3 control signals. Comparing with the original 64-bit array multiplier which requires 4032 Full Adders and 4096 two-input AND gates, the hardware overhead is very small. With additional metal lines for interconnections, the hardware overhead will not increase the chip area. In other words, the high reconfigurability of the developed circuit is achieved with negligible hardware overhead and virtually no performance overhead. The reconfigurable structure continues to use the conventional array multiplier with minor changes. This study also presents the design methodology of reconfigurable multiplier-accumulators (AxB+C)for signal processing applications.
|出版狀態||已出版 - 2004|
|事件||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan|
持續時間: 6 12月 2004 → 9 12月 2004
|???event.eventtypes.event.conference???||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology|
|期間||6/12/04 → 9/12/04|