Design of Low Voltage Vertical Channel Face-tunneling TFET Using Ge/SiGe Materials and Its SRAM Circuit Performance

Akancha Gupta, C. K. Chiang, W. Y. Yang, E. R. Hsieh, Steve S. Chung

研究成果: 書貢獻/報告類型會議論文篇章同行評審

5 引文 斯高帕斯(Scopus)

摘要

A novel vertical channel face-tunneling field effect transistor (VC-TFET) using Ge/SiGe material is proposed in this paper. The proposed device structure enhances the on-state drive current without increasing the device footprint and also provides lower off-state leakage current, steeper sub-threshold slope and higher Ion/Ioff current ratio compared to the other TFETs. The design of SiGe-material in the drain region suppresses the leakage current, and the channel region with small bandgap Ge enhances the tunneling current. Additionally, the complementary vertical channel TFET is also used to demonstrate the SRAM circuit performance for low power application. Novel SRAM topologies are proposed to eliminate the read disturb and enhance the RSNM/WSNM of SRAM.

原文???core.languages.en_GB???
主出版物標題2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
發行者Institute of Electrical and Electronics Engineers Inc.
頁面132-133
頁數2
ISBN(電子)9781728142326
DOIs
出版狀態已出版 - 8月 2020
事件2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan
持續時間: 10 8月 202013 8月 2020

出版系列

名字2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

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???event.eventtypes.event.conference???2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
國家/地區Taiwan
城市Hsinchu
期間10/08/2013/08/20

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