Design-for-debug layout adjustment for FIB probing and circuit editing

Kuo An Chen, Tsung Wei Chang, Meng Chen Wu, Mango C.T. Chao, Jing Yang Jou, Sonair Chen

研究成果: 雜誌貢獻會議論文同行評審

1 引文 斯高帕斯(Scopus)


While the technology node continually and aggressively scales, the resolution of FIB techniques does not scale as fast. Thus, the percentage of nets which can be observed or repaired through FIB probing or circuit editing is significantly decreased for advanced process technologies, which limits the candidates that can be physically examined through the FIB techniques during the debugging process. This paper introduces a design-for-debug framework which can adjust the layout to increase the FIB observable rate and the FIB repairable rate for its signals. The layout adjustment is made through pre-defined simple operations subject to the design rules and the timing constraints. Hence, the proposed framework does not require a complicated router as its core and can be applied in conjunction with any commercial APR tool. The experimental result based on an 90nm technology has demonstrated that the proposed DFD framework can effectively increase the FIB observable and repairable rates under different parameter settings while the overall area and circuit performance remain the same.

期刊Proceedings - International Test Conference
出版狀態已出版 - 2011
事件International Test Conference 2011, ITC 2011 - Anaheim, CA, United States
持續時間: 18 9月 201123 9月 2011


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