Design and VLSI implementation of MPEG audio decoder

Tsung Han Tsai; Thou Ho Chen; Liang Gee Chen

Design and VLSI implementation of MPEG audio decoder

Tsung Han Tsai, Thou Ho Chen, Liang Gee Chen

電機工程學系

研究成果: 會議貢獻類型 › 會議論文 › 同行評審

摘要

The paper presents a chip design for MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced into half of the original one, and the storage demand too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using the structure silicon compiler in the Genesil system, with 0.8-μm CMOS technology.

原文	???core.languages.en_GB???
頁面	206-210
頁數	5
出版狀態	已出版 - 1995
事件	Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan 持續時間: 31 5月 1995 → 2 6月 1995

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications
城市	Taipei, Taiwan
期間	31/05/95 → 2/06/95

引用此

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AU - Chen, Thou Ho

AU - Chen, Liang Gee

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N2 - The paper presents a chip design for MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced into half of the original one, and the storage demand too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using the structure silicon compiler in the Genesil system, with 0.8-μm CMOS technology.

AB - The paper presents a chip design for MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced into half of the original one, and the storage demand too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using the structure silicon compiler in the Genesil system, with 0.8-μm CMOS technology.

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M3 - 會議論文

AN - SCOPUS:0029544418

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T2 - Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications

Y2 - 31 May 1995 through 2 June 1995

ER -

Design and VLSI implementation of MPEG audio decoder

摘要

???event.eventtypes.event.conference???

指紋

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