Design and analysis of CMOS low-phase-noise low-jitter subharmonically injection-locked VCO with FLL self-alignment technique

Hong Yeh Chang, Chun Ching Chan, Ian Yi En Shen, Yen Liang Yeh, Shu Yan Huang

研究成果: 雜誌貢獻期刊論文同行評審

13 引文 斯高帕斯(Scopus)

摘要

Design and analysis of low-phase-noise low-jitter subharmonically injection-locked voltage-controlled oscillator (VCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90-nm CMOS process. The issue of the narrow locking range for the subharmonically injection-locked VCO (SILVCO) can be resolved over the variations, especially for high subharmonic number and millimeter-wave band, since the control voltage is adaptively adjusted using the proposed innovative method to refer to the subharmonic input frequency. A theoretical model of the SILVCO with FLL self-alignment technique is addressed for the design consideration and phase noise evaluation. With a subharmonic number of 16, the operation frequency of the proposed K-band circuit is from 24 to 26.1 GHz. The measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are -114.3 dBc/Hz and 56.6 fs, respectively. As the temperature is from 20 °C to 70 °C, the measured deviations of output power, phase noise, and jitter are within 2 dB, 3 dB, and 67 fs, respectively. This paper demonstrates excellent performance and good robustness, and it can be compared with the previously reported state-of-the-art clock generators in silicon-based technologies.

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文章編號7748445
頁(從 - 到)4632-4645
頁數14
期刊IEEE Transactions on Microwave Theory and Techniques
64
發行號12
DOIs
出版狀態已出版 - 12月 2016

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