Design and Analysis of a V-Band CMOS Sextuple SILVCO Using Transformer and Cascade-Series Coupling With a Frequency-Tracking Loop

A low-phase-noise local oscillator (LO) is a crucial component in communication systems. However, the design challenge of the LO significantly increases as the operating frequency rises. This paper focuses on the design and analysis of a V -band CMOS sextuple sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with a frequency-tracking loop (FTL). To further enhance the locking range and efficiently generate high-order harmonic components, a cascade-series coupling injector is proposed for employment in the SILVCO. The design methodology of the proposed circuit is thoroughly presented, accompanied by analysis and calculated results. The SILVCO with FTL is implemented using a 90-nm CMOS process. With a sub-harmonic number of 6 and a dc power consumption of 23 mW, the measured output frequency ranges from 50.8 to 53.4 GHz, achieving a differential output power close to 0 dBm. The measured phase noise at a 1 MHz offset and the rms jitter integrated from 1 kHz to 10 MHz are both lower than -109.4 dBc/Hz and 43 fs, respectively.