TY - JOUR
T1 - Design and analysis of 0.5-ft bandwidth thas with resolution enhancement techniques in 0.18-μm sige process
AU - Lin, Yu An
AU - Huang, Guan Lin
AU - Yeh, Ya Che
AU - Chang, Hong Yeh
N1 - Publisher Copyright:
© 2013 IEEE.
PY - 2019
Y1 - 2019
N2 - This paper presents the design and analysis of microwave and millimeter-wave (MMW) high-linear track-and-hold amplifiers (THAs) for high-speed data conversion systems. The silicon germanium (SiGe) process utilized in the proposed circuits is analyzed in detail and its several merits are demonstrated, including operating speed, linearity, and resolution. Bandwidth extension techniques, such as peaking, Darlington, and distributed topologies, are adopted to further enhance the operating speed of the proposed THAs up to a 0.5-unity current gain frequency (t) of the transistor. The switched emitter-follower (SEF) as well as the switched capacitor (SC) track-and-hold (T/H) stages are modified using pedestal error reduction techniques, including a cascode stage and differential cancellation, to further enhance the overall resolution of the THAs. The proposed cascoded SEF-based T/H circuit with a modified Darlington-based input buffer has a track-mode bandwidth of up to 0.5-t, a maximum spurious-free dynamic range (SFDR) of 45.1 dBc, and dc power consumption of 94.3 mW. Moreover, the proposed differential cancellation SC-based T/H circuit with an input buffer based on the distributed bandwidth extension technique exhibits an operating speed of up to 0.32-t, an SFDR of 47.9 dBc, and dc power consumption of 180.1 mW. Both proposed THAs are suitable for low-power, high-speed MMW conversion systems without incurring a high cost. Moreover, by using the proposed design methodology, a sampling rate up to tens of gigahertz can be easily achieved with time-interleaved architecture.
AB - This paper presents the design and analysis of microwave and millimeter-wave (MMW) high-linear track-and-hold amplifiers (THAs) for high-speed data conversion systems. The silicon germanium (SiGe) process utilized in the proposed circuits is analyzed in detail and its several merits are demonstrated, including operating speed, linearity, and resolution. Bandwidth extension techniques, such as peaking, Darlington, and distributed topologies, are adopted to further enhance the operating speed of the proposed THAs up to a 0.5-unity current gain frequency (t) of the transistor. The switched emitter-follower (SEF) as well as the switched capacitor (SC) track-and-hold (T/H) stages are modified using pedestal error reduction techniques, including a cascode stage and differential cancellation, to further enhance the overall resolution of the THAs. The proposed cascoded SEF-based T/H circuit with a modified Darlington-based input buffer has a track-mode bandwidth of up to 0.5-t, a maximum spurious-free dynamic range (SFDR) of 45.1 dBc, and dc power consumption of 94.3 mW. Moreover, the proposed differential cancellation SC-based T/H circuit with an input buffer based on the distributed bandwidth extension technique exhibits an operating speed of up to 0.32-t, an SFDR of 47.9 dBc, and dc power consumption of 180.1 mW. Both proposed THAs are suitable for low-power, high-speed MMW conversion systems without incurring a high cost. Moreover, by using the proposed design methodology, a sampling rate up to tens of gigahertz can be easily achieved with time-interleaved architecture.
KW - Cmos/sige rfic
KW - High-speed analog ic design
KW - Microwave integrated circuits (ics)
KW - Mixed signal design
KW - Sampling circuits
UR - http://www.scopus.com/inward/record.url?scp=85063614117&partnerID=8YFLogxK
U2 - 10.1109/ACCESS.2019.2903887
DO - 10.1109/ACCESS.2019.2903887
M3 - 期刊論文
AN - SCOPUS:85063614117
SN - 2169-3536
VL - 7
SP - 33024
EP - 33037
JO - IEEE Access
JF - IEEE Access
M1 - 8663287
ER -