Delay-optimal technology mapping for hard-wired non-homogeneous FPGAs

Keyphrases

• Technology Mapping 100%
• Delay Optimal 100%
• Hardwired 100%
• Optimal Technology 100%
• CPU Time 33%
• Xilinx 33%
• Two Dimensional 16%
• Wired Network 16%
• Area-efficient 16%
• Homogeneous Structure 16%
• Logic Block 16%
• Connection Efficiency 16%
• Block Architecture 16%
• Node Cut 16%
• Labeling Approach 16%
• Flow Map 16%
• Mapping Algorithm 16%

Computer Science

• Technology Mapping 100%
• Field Programmable Gate Arrays 100%
• Experimental Result 50%
• Mapping Algorithm 50%
• Wired Connection 50%