DC-16 GHz GaAs track-And-hold amplifier using sampling rate and linearity enhancement techniques

Y. A. Lin; H. Y. Chang; Y. C. Wang

doi:10.1049/el.2017.3372

DC-16 GHz GaAs track-And-hold amplifier using sampling rate and linearity enhancement techniques

Y. A. Lin, H. Y. Chang, Y. C. Wang

電機工程學系

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A DC-16 GHz track-And-hold amplifier (THA) using 0.15-μm enhancement-mode GaAs pseudomorphic high-electron mobility transistor process is presented. A switched source follower (SSF) track-And-hold (T/H) stage is modified to enhance the sampling rate and linearity. The input-dependent timing jitter is highly reduced using the modified topology as compared to the conventional SSF T/H stage. Moreover, the even harmonics are successfully suppressed using the differential topology, and the spurious-free dynamic range (SFDR) and total harmonic distortion (THD) are improved. To widen bandwidth (BW), the input and output buffers are designed using the distributed amplifier and source follower, respectively. With a sampling rate of 13.5 GS/s, the proposed THA features a measured 3-dB BW of 16 GHz, an SFDR of 46 dB, and a THD of -45 dB.

原文	???core.languages.en_GB???
頁（從 - 到）	83-85
頁數	3
期刊	Electronics Letters
卷	54
發行號	2
DOIs	https://doi.org/10.1049/el.2017.3372
出版狀態	已出版 - 25 1月 2018

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10.1049/el.2017.3372

微波及毫米波量測儀器系統之高性能前端積體電路開發(2/3)
Chang, H.-Y. (PI)
1/08/17 → 31/07/18
研究計畫: Research
應用於小型無人飛行載具之W頻段雷達前端積體電路研製(1/3)
Chang, H.-Y. (PI)
1/08/17 → 31/07/18
研究計畫: Research

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title = "DC-16 GHz GaAs track-And-hold amplifier using sampling rate and linearity enhancement techniques",

abstract = "A DC-16 GHz track-And-hold amplifier (THA) using 0.15-μm enhancement-mode GaAs pseudomorphic high-electron mobility transistor process is presented. A switched source follower (SSF) track-And-hold (T/H) stage is modified to enhance the sampling rate and linearity. The input-dependent timing jitter is highly reduced using the modified topology as compared to the conventional SSF T/H stage. Moreover, the even harmonics are successfully suppressed using the differential topology, and the spurious-free dynamic range (SFDR) and total harmonic distortion (THD) are improved. To widen bandwidth (BW), the input and output buffers are designed using the distributed amplifier and source follower, respectively. With a sampling rate of 13.5 GS/s, the proposed THA features a measured 3-dB BW of 16 GHz, an SFDR of 46 dB, and a THD of -45 dB.",

author = "Lin, {Y. A.} and Chang, {H. Y.} and Wang, {Y. C.}",

note = "Funding Information: This work was supported in part by the Ministry of Science and Technology (MOST), Taiwan, under Grants MOST 105-2221-E-008-020-MY3 and MOST 106-2628-E-008-001-MY3, and by Chip Implementation Center (CIC), Taiwan. The chip was fabricated by WIN Semiconductors Corporation, Taiwan.",

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AU - Lin, Y. A.

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AU - Wang, Y. C.

N1 - Funding Information: This work was supported in part by the Ministry of Science and Technology (MOST), Taiwan, under Grants MOST 105-2221-E-008-020-MY3 and MOST 106-2628-E-008-001-MY3, and by Chip Implementation Center (CIC), Taiwan. The chip was fabricated by WIN Semiconductors Corporation, Taiwan.

PY - 2018/1/25

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N2 - A DC-16 GHz track-And-hold amplifier (THA) using 0.15-μm enhancement-mode GaAs pseudomorphic high-electron mobility transistor process is presented. A switched source follower (SSF) track-And-hold (T/H) stage is modified to enhance the sampling rate and linearity. The input-dependent timing jitter is highly reduced using the modified topology as compared to the conventional SSF T/H stage. Moreover, the even harmonics are successfully suppressed using the differential topology, and the spurious-free dynamic range (SFDR) and total harmonic distortion (THD) are improved. To widen bandwidth (BW), the input and output buffers are designed using the distributed amplifier and source follower, respectively. With a sampling rate of 13.5 GS/s, the proposed THA features a measured 3-dB BW of 16 GHz, an SFDR of 46 dB, and a THD of -45 dB.

AB - A DC-16 GHz track-And-hold amplifier (THA) using 0.15-μm enhancement-mode GaAs pseudomorphic high-electron mobility transistor process is presented. A switched source follower (SSF) track-And-hold (T/H) stage is modified to enhance the sampling rate and linearity. The input-dependent timing jitter is highly reduced using the modified topology as compared to the conventional SSF T/H stage. Moreover, the even harmonics are successfully suppressed using the differential topology, and the spurious-free dynamic range (SFDR) and total harmonic distortion (THD) are improved. To widen bandwidth (BW), the input and output buffers are designed using the distributed amplifier and source follower, respectively. With a sampling rate of 13.5 GS/s, the proposed THA features a measured 3-dB BW of 16 GHz, an SFDR of 46 dB, and a THD of -45 dB.

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DO - 10.1049/el.2017.3372

M3 - 期刊論文

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SN - 0013-5194

VL - 54

SP - 83

EP - 85

JO - Electronics Letters

JF - Electronics Letters

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DC-16 GHz GaAs track-And-hold amplifier using sampling rate and linearity enhancement techniques

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微波及毫米波量測儀器系統之高性能前端積體電路開發(2/3)

應用於小型無人飛行載具之W頻段雷達前端積體電路研製(1/3)

引用此