Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing

Iris Hui Ru Jiang, Yao Wen Chang, Jing Yang Jou

研究成果: 雜誌貢獻期刊論文同行評審

49 引文 斯高帕斯(Scopus)

摘要

Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1-MB memory and 19.4-min runtime to achieve the precision of within 1% error on a SUN Sparc Ultra-I workstation.

原文???core.languages.en_GB???
頁(從 - 到)999-1010
頁數12
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
19
發行號9
DOIs
出版狀態已出版 - 9月 2000

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