Critical path monitor enabled dynamic voltage scaling for graceful degradation in sub-threshold designs

Yu Guang Chen, Tao Wang, Kuan Yu Lai, Wan Yu Wen, Yiyu Shi, Shih Chieh Chang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

7 引文 斯高帕斯(Scopus)

摘要

Sub-threshold designs play an important role in energyconstrained applications. In those designs, path delays depend exponentially on threshold voltage/temperature. As such, dynamic configurations at runtime are desired for best trade-off between operating power and performance. Unfortunately, most existing works only consider either process or temperature variations but not both, resulting in sub-optimal configurations or even functional failures. Moreover, little study has been performed on the graceful degradation of sub-threshold designs, which is important in the presence of drastic delay variations. Towards this, we present a novel critical path monitor based dynamic voltage scaling scheme. Considering both process and temperature variations, it minimizes the operating power under a given timing error probability (TEP) bound. An exact method to decide the optimal switching thresholds is also proposed. Experimental results on 45nm industrial designs show that with only 1% TEP, our scheme can reduce the operating power by up to 75.3% compared with the constant voltage scheme. To the best of the authors' knowledge, this is the very first work on dynamic configuration for graceful degradation in sub-threshold designs.

原文???core.languages.en_GB???
主出版物標題DAC 2014 - 51st Design Automation Conference, Conference Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(列印)9781479930173
DOIs
出版狀態已出版 - 2014
事件51st Annual Design Automation Conference, DAC 2014 - San Francisco, CA, United States
持續時間: 2 6月 20145 6月 2014

出版系列

名字Proceedings - Design Automation Conference
ISSN(列印)0738-100X

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???event.eventtypes.event.conference???51st Annual Design Automation Conference, DAC 2014
國家/地區United States
城市San Francisco, CA
期間2/06/145/06/14

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