Cost-effective TAP-controlled serialized compressed scan architecture for 3D stacked ICs

Chen An Chen, Yee Wen Chen, Chun Lung Hsu, Ming Hsueh Wu, Kun Lun Luo, Bing Chuan Bai, Liang Chia Cheng

研究成果: 雜誌貢獻會議論文同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the 3D stacked ICs (3D-SICs) configuration. Additionally, a serialized compressed signal generator (SCSG) design is also developed of the proposed scheme to generate the corresponding controlled signals for SCSA to ensure the test cost reduction. Experimental results and comparisons show that the proposed scheme can effectively achieve the good performance in test pin count and test time reduction with little extra hardware overhead penalty.

原文???core.languages.en_GB???
文章編號6690625
頁(從 - 到)107-108
頁數2
期刊Proceedings of the Asian Test Symposium
DOIs
出版狀態已出版 - 2013
事件2013 22nd Asian Test Symposium, ATS 2013 - Yilan, Taiwan
持續時間: 18 11月 201321 11月 2013

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