MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. The first type is regular but computation-intensive such as filtering, matrixing, degrouping, and transformation operations. The second type is not regular but computation-intensive such as parsing bitstream, setting operation mode and controlling of all system operations. Based on standard cell design technique, the chip size is 6.4×6.4 mm2, and the tested chip can run at maximum 43.5 MHz clock rate.
|頁（從 - 到）||361-369|
|期刊||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|出版狀態||已出版 - 1999|
|事件||1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan|
持續時間: 20 10月 1999 → 22 10月 1999