Chip design of MFCC extraction for speech recognition

The mel frequency cepstral coefficient (MFCC) is one of the most important features required among various kinds of speech applications. In this paper, the first chip for speech features extraction based on MFCC algorithm is proposed. The chip is implemented as an intellectual property, which is suitable to be adopted in a speech recognition system on a chip. The computational complexity and memory requirement of MFCC algorithm are analyzed in detail and improved greatly. The hybrid table look-up scheme is presented to deal with the elementary function value in the MFCC algorithm. Fixed-point arithmetic is adopted to reduce the cost under the accuracy studies of finite word length effect. Finally, the area-efficient design is implemented successfully into the single Xilinx XC4062XL FPGA.