Chip design of mel frequency cepstral coefficients for speech recognition

The mel frequency cepstral coefficients (MFCC) is one of the mast important features, which is required among various kinds of speech applications. The chip for speech features extraction based on the MFCC algorithm is first proposed. The chip is designed with area efficient consideration and can achieve the following: (1) the reduction of table size and multiplication complexity by means of the symmetric property of the cosine function, (2) the decrease of the multiplication load and required constant memory in the calculation of the weighted energy spectrum by applying the mapping relationship between the mel scale and the frequency scale, (3) the minimization of the look-up table size for logarithm operations by modifying the partitioned table look-up method. The chip is fabricated with 0.6 μm double-metal CMOS technology. It contains approximately 10,000 gates occupying 3.2×3.3 mm² area and the maximum clock rate is 50 MHz.