Bit error rate measurement system for RF integrated circuits

Hsu Feng Hsiao, Shuw Guann Lin, Sy Haur Su, Chih Ho Tu, Da Chiang Chang, Ying Zong Juang, Hwann Kaeo Chiou

研究成果: 書貢獻/報告類型會議論文篇章同行評審

3 引文 斯高帕斯(Scopus)

摘要

This paper proposes a bit error rate (BER) measurement system utilizing vector signal analyzer (VSA) instrument built-in analog digital converter (ADC) and ideal digital baseband receiver of VSA software for RF integrated circuits (RFICs) such as RF amplifier, RF mixer and RF receiver. Usually, BER performance is estimated in transceiver with built-in digital baseband circuits. In the past, RF designers could not estimate RFICs effect to BER test without digital baseband circuits and vice versa for digital baseband designers. It is helpful to understand RFICs without digital baseband circuits to BER test can reduce certain risk before integrating RFICs with digital baseband circuits. Therefore, an implementation of output signal to noise ratio (SNR) calibration in a specified bandwidth and measurement method combined VSA instrument, VSA software and Advanced Design System (ADS) is used for BER measurement.

原文???core.languages.en_GB???
主出版物標題2012 IEEE I2MTC - International Instrumentation and Measurement Technology Conference, Proceedings
頁面2381-2384
頁數4
DOIs
出版狀態已出版 - 2012
事件2012 IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2012 - Graz, Austria
持續時間: 13 5月 201216 5月 2012

出版系列

名字2012 IEEE I2MTC - International Instrumentation and Measurement Technology Conference, Proceedings

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???event.eventtypes.event.conference???2012 IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2012
國家/地區Austria
城市Graz
期間13/05/1216/05/12

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