TY - JOUR
T1 - Beyond write-reduction consideration
T2 - A wear-leveling-enabled b+-tree indexing scheme over an nvram-based architecture
AU - Dharamjeet,
AU - Chen, Tseng Yi
AU - Chang, Yuan Hao
AU - Wu, Chun Feng
AU - Lee, Chi Heng
AU - Shih, Wei Kuan
N1 - Publisher Copyright:
© 2021 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.
PY - 2021/12/1
Y1 - 2021/12/1
N2 - Recently, nonvolatile random-access memory (NVRAM) has been regarded as the most up-and-coming main memory technology in embedded and Internet-of-Things (IoT) systems due to its attractive features: Zero-static power consumption and high memory cell density. However, the endurance issue as a "nightmare" always haunts NVRAM system developers. Worse still, NVRAM's lifespan will wear out soon in embedded applications because their data management systems usually utilize an indexing scheme to maintain small data. Plus, a node structure within the indexing scheme will be frequently updated because of data creation and deletion. Therefore, many previous works rethink B+-tree indexing scheme on an NVRAM-based system. The most previous studies focused on reducing the amount of write traffic to memory. Unfortunately, they are failed to extend the NVRAM lifespan because their solution cannot evenly distribute the amount of write traffic to each memory cell. Additionally, prior solutions have not considered that all nodes within B+-tree indexing structure have different update frequencies. Based on such the observation, this work proposes a wear-leveling-aware B+-tree design, namely, waB+-tree, to consider the update frequency of each node within the B+-tree structure, so as to evenly scatter the amount of write traffic to the NVRAM cells. According to our experiments, the proposed waB+-tree shows the encouraging results of endurance improvement.
AB - Recently, nonvolatile random-access memory (NVRAM) has been regarded as the most up-and-coming main memory technology in embedded and Internet-of-Things (IoT) systems due to its attractive features: Zero-static power consumption and high memory cell density. However, the endurance issue as a "nightmare" always haunts NVRAM system developers. Worse still, NVRAM's lifespan will wear out soon in embedded applications because their data management systems usually utilize an indexing scheme to maintain small data. Plus, a node structure within the indexing scheme will be frequently updated because of data creation and deletion. Therefore, many previous works rethink B+-tree indexing scheme on an NVRAM-based system. The most previous studies focused on reducing the amount of write traffic to memory. Unfortunately, they are failed to extend the NVRAM lifespan because their solution cannot evenly distribute the amount of write traffic to each memory cell. Additionally, prior solutions have not considered that all nodes within B+-tree indexing structure have different update frequencies. Based on such the observation, this work proposes a wear-leveling-aware B+-tree design, namely, waB+-tree, to consider the update frequency of each node within the B+-tree structure, so as to evenly scatter the amount of write traffic to the NVRAM cells. According to our experiments, the proposed waB+-tree shows the encouraging results of endurance improvement.
KW - B+-tree structure
KW - Endurance
KW - Indexing scheme
KW - Nonvolatile random-access memory (NVRAM)-based system
UR - http://www.scopus.com/inward/record.url?scp=85099215642&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2021.3049677
DO - 10.1109/TCAD.2021.3049677
M3 - 期刊論文
AN - SCOPUS:85099215642
SN - 0278-0070
VL - 40
SP - 2455
EP - 2466
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 12
ER -