Beyond write-reduction consideration: A wear-leveling-enabled b+-tree indexing scheme over an nvram-based architecture

Dharamjeet, Tseng Yi Chen, Yuan Hao Chang, Chun Feng Wu, Chi Heng Lee, Wei Kuan Shih

研究成果: 雜誌貢獻期刊論文同行評審

摘要

Recently, nonvolatile random-access memory (NVRAM) has been regarded as the most up-and-coming main memory technology in embedded and Internet-of-Things (IoT) systems due to its attractive features: Zero-static power consumption and high memory cell density. However, the endurance issue as a "nightmare" always haunts NVRAM system developers. Worse still, NVRAM's lifespan will wear out soon in embedded applications because their data management systems usually utilize an indexing scheme to maintain small data. Plus, a node structure within the indexing scheme will be frequently updated because of data creation and deletion. Therefore, many previous works rethink B+-tree indexing scheme on an NVRAM-based system. The most previous studies focused on reducing the amount of write traffic to memory. Unfortunately, they are failed to extend the NVRAM lifespan because their solution cannot evenly distribute the amount of write traffic to each memory cell. Additionally, prior solutions have not considered that all nodes within B+-tree indexing structure have different update frequencies. Based on such the observation, this work proposes a wear-leveling-aware B+-tree design, namely, waB+-tree, to consider the update frequency of each node within the B+-tree structure, so as to evenly scatter the amount of write traffic to the NVRAM cells. According to our experiments, the proposed waB+-tree shows the encouraging results of endurance improvement.

原文???core.languages.en_GB???
頁(從 - 到)2455-2466
頁數12
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
40
發行號12
DOIs
出版狀態已出版 - 1 12月 2021

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