Arbitrary duty cycle synchronous mirror delay circuits design

Cheng Liang Hung, Chen Lung Wu, Kuo Hsing Cheng

研究成果: 會議貢獻類型會議論文同行評審

7 引文 斯高帕斯(Scopus)

摘要

An arbitrary duty cycle synchronous mirror delay (SMD) circuit is proposed in this paper. The conventional SMD can be locked in 2 clock cycles, but it just can accept only the narrow pulse clock signal, which will greatly restrict the application of the circuits. The modified TSPC DFF is used in the proposed SMD circuit to detect clock edge. Therefore, the proposed SMD circuit not only can be locked in 2 clock cycle time but also can accept arbitrary duty cycle clocks. Moreover, it can detect a small dead zone and makes the new circuit has better jitter performance and lower static phase error. An experiment chip was fabricated in 0.18μm CMOS process. With a 1.8 V supply voltage, the measure results show that the proposed circuits can be operated from 450MHz to 750MHz. When the input clock frequency is 750MHz, the measured power dissipation was 9mW. In addition, the peak-to-peak and rms jitters were 24ps and 2.94ps, respectively.

原文???core.languages.en_GB???
頁面283-286
頁數4
DOIs
出版狀態已出版 - 2006
事件2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China
持續時間: 13 11月 200615 11月 2006

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???event.eventtypes.event.conference???2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
國家/地區China
城市Hangzhou
期間13/11/0615/11/06

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