每年專案
摘要
This paper presents a high power, high efficiency, low phase noise power oscillator. The oscillator is designed with WIN™ 0.25 μm GaN process with 220 µm gate width. Self-bias effect caused by gate resistor was investigated and found that the use of proper gate resistance improved the DC-to-RF efficiency. With 8-V DC supply voltage, the power oscillator delivers a 19.6-dBm output power at-2.5 V gate bias, and 14.86 mA DC current that achieve a 21.9% DC-RF efficiency. Phase noise was measured to be-118.02 dBc/Hz at 1-MHz and-130 dBc/Hz at 10-MHz offset frequencies from 9.81 GHz oscilla-tion frequency. The chip size with on chip RF choke and PAD is 1.5 × 1 mm2.
原文 | ???core.languages.en_GB??? |
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頁(從 - 到) | 45-50 |
頁數 | 6 |
期刊 | International Journal of Electrical Engineering |
卷 | 27 |
發行號 | 2 |
DOIs | |
出版狀態 | 已出版 - 4月 2020 |
指紋
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