A singular-value-decomposition (SVD) processor having adjustable precision for 8 \times 8 multiple-input multiple-output precoding systems supporting up to 256-quadrature amplitude modulation (QAM) is designed and implemented. The memory-based architecture that consists of eight processing elements, each having two coordinate rotation digital computer modules, is employed. Golub-Reinsch SVD (GR-SVD) algorithm with Rayleigh quotient shift is used. Thus, two-phase operations are performed including bidiagonalization and implicit shifted QR for diagonalization. The split, deflation, and shift techniques of GR-SVD are helpful to accelerate the diagonalization and reduce the computation complexity. To cover the precision requirements for compact 256-QAM constellation and spatially correlated channels, hybrid datapath representations are used. The threshold for split and deflation can be adjusted and thus the precision of the SVD processor is variable according to the requirements. Although the high precision results in a large gate count, this SVD processor in 40-nm CMOS technology can complete the decomposition of an 8 \times 8 matrix in 313 clock cycles averagely and is able to provide a throughput rate of 591K matrix/s with good power efficiency.
|頁（從 - 到）||2572-2583|
|期刊||IEEE Transactions on Circuits and Systems I: Regular Papers|
|出版狀態||已出版 - 7月 2019|
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