An optimum algorithm for compacting error traces for efficient functional debugging

Chia Chih Yen, Jing Yang Jou

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

Diagnosing counterexamples with error traces has acted as one of the most critical steps in functional verification. Unfortunately, error traces are normally very lengthy such that designers need to spend considerable effort to understand them. To alleviate designers ' burden for debugging, we present a SAT-based algorithm for reducing the lengths of error traces. The algorithm performs the paradigm of binary search algorithm to halve the search space recursively. Furthermore, it applies a novel theorem to guarantee to gain the shortest lengths for the error traces. Experimental results demonstrate that our approach greatly surpasses previous work and indeed has the optimum solutions.

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主出版物標題Proceedings - Tenth Annual IEEE International High Level Design Validation and Test Workshop, HLDVT'05
頁面177-183
頁數7
DOIs
出版狀態已出版 - 2005
事件Tenth Annual IEEE International High Level Design Validation and Test Workshop, HLDVT'05 - Napa Valley, CA, United States
持續時間: 30 11月 20052 12月 2005

出版系列

名字Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
2005
ISSN(列印)1552-6674

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???event.eventtypes.event.conference???Tenth Annual IEEE International High Level Design Validation and Test Workshop, HLDVT'05
國家/地區United States
城市Napa Valley, CA
期間30/11/052/12/05

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