@inproceedings{b2719daa4a884a299c7262d752113f20,
title = "An IP-based design to achieve power reduction",
abstract = "In this chapter, an IP-based design for power reduction on a one- dimension, lifting-based discrete wavelet transform (DWT) is presented. The prototype architecture is coded in VerilogHDL and simulated using Quartus-II to verify the function. Based on this prototype architecture, a low-power operator (adder and subtractor) IP, which is designed based on a full-custom design methodology, plays a role in replacing the main operations. The simulation result shows that power consumption can be reduced by 16.31%. The architecture can be used as an independent IP core of a wavelet-based application.",
keywords = "Discrete wavelet transform, IP, VerilogHDL",
author = "Hsieh, {Chin Fa} and Tsai, {Tsung Han} and Lai, {Chih Hung}",
note = "Publisher Copyright: {\textcopyright} Springer International Publishing Switzerland 2016.; 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 ; Conference date: 19-12-2014 Through 21-12-2014",
year = "2016",
doi = "10.1007/978-3-319-17314-6_63",
language = "???core.languages.en_GB???",
isbn = "9783319173139",
series = "Lecture Notes in Electrical Engineering",
publisher = "Springer Verlag",
pages = "493--499",
editor = "Jengnan Juang",
booktitle = "Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014",
}