An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring high speed, ultra-low power, and low voltage operation

E. R. Hsieh, C. H. Chuang, Steve S. Chung

研究成果: 書貢獻/報告類型會議論文篇章同行評審

1 引文 斯高帕斯(Scopus)

摘要

For the first time, a new 1T1R of volatile memory based on the interfacial dipole flipping mechanism, named as Dipole Dynamic Random Access Memory (DiRAM), has been reported. It features 4ns per bit of dipole switching time, larger than 109 of endurance, and 10 seconds of retention with reasonable positive and negative resistance window, low operation voltages with bit line at 0.8V and word line at 0.2V, and around 1 nano-Watt per bit of operation power. DiRAM is also easy to be integrated with state-of-The-Art CMOS technology. The results have shown that this volatile memory may be a potential candidate for the next generation DRAM technology.

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主出版物標題2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467394789
DOIs
出版狀態已出版 - 27 5月 2016
事件International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016 - Hsinchu, Taiwan
持續時間: 25 4月 201627 4月 2016

出版系列

名字2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016

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???event.eventtypes.event.conference???International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
國家/地區Taiwan
城市Hsinchu
期間25/04/1627/04/16

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