An experimental study on high-frequency substrate noise isolation in BiCMOS technology

Ping Chun Yeh, Hwann Kaeo Chiou, Chwan Ying Lee, John Yeh, Denny Tang, John Chern

研究成果: 雜誌貢獻期刊論文同行評審

9 引文 斯高帕斯(Scopus)


In this letter, four substrate noise isolation structures in standard 0.18-μ SiGe bipolar CMOS technology were investigated using S-parameter measurements. The experimental and simulated results on different isolation structures, such as triple-well p-n junction isolated walls, deep trench isolation, and double P+ guard-ring structures, are presented. Each element in the equivalent circuits has been calculated or fitted based on the parasitic resistance, capacitance, and physical dimensions using the device simulator MEDICI and the measured results of the test patterns. The proposed structure B significantly reduced substrate noise below -70 dB up to 20 GHz. The proposed structure C with an extra triple-well junction achieved the best isolation at the lower frequency range, in which S21 was less than -71 dB from 50 MHz to 10.05 GHz, and -56 dB from 10.05 to 20.05 GHz. The measured results showed an excellent agreement with the calculations. Structure B is good enough and is recommended for a general-purpose RF circuit design, whereas structure C can be used in a highly sensitive RF circuit block below 10 GHz.

頁(從 - 到)255-258
期刊IEEE Electron Device Letters
出版狀態已出版 - 3月 2008


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