An electrical testing method for blind through silicon vias (TSVs) for 3D IC integration

This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.