An efficient logic extraction algorithm using partitioning and circuit encoding

Lily Huang, Tai Ying Jiang, Jing Yang Jou, Heng Liang Huang

研究成果: 雜誌貢獻會議論文同行評審

2 引文 斯高帕斯(Scopus)


Nowadays, finding subcircuits in a larger circuit is primarily solved by using various heuristics based on graph isomorphism. These approaches are addressed on identifying one specific subcircuit at each time and may take numerous runs if many subcircuits need to be extracted. Therefore, they are not quite suitable for converting the whole circuit represented at transistor-level to a gate-level netlist. We present a logic extraction approach based on dc-connected component (DCC) partition and modified circuit-encoding algorithm to extract all kinds of subscircuits from the input circuit concurrently such that we can map each subcircuit represented as transistor level netlist to its corresponding logic gate. This mapping relation can be exploited to speed up the simulation of large circuits. Experiments on several real circuits, including sequential logic ones and combination logic ones, show the near-linear performance in run time and memory usage.

頁(從 - 到)V-249-V-252
期刊Proceedings - IEEE International Symposium on Circuits and Systems
出版狀態已出版 - 2004
事件2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
持續時間: 23 5月 200426 5月 2004


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