An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

Keyphrases

• 3D IC 100%
• Memory BIST 100%
• On-chip Test 100%
• TSV Test 100%
• Area Overhead 66%
• Testing Framework 66%
• Stacked IC 66%
• On chip 33%
• Test Pattern 33%
• Integrated Circuits 33%
• Low Area 33%
• Test Time Reduction 33%
• Heterogeneous Integrated 33%
• Extra Time 33%
• On-chip Testing 33%
• IC Test 33%
• 3D IC Design 33%
• Connection Length 33%

Engineering

• Built-in Self Test 100%
• Test Framework 100%
• Area Overhead 66%
• Experimental Result 33%
• Test Time 33%
• Test Procedure 33%
• Good Performance 33%
• Integrated Circuit Design 33%
• Integrated Circuit 33%

Computer Science

• Test Framework 100%
• Experimental Result 33%
• Input/Output 33%
• Good Performance 33%
• Integrated Circuit 33%