An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

Liang Che Li; Wen Hsuan Hsu; Kuen Jong Lee; Chun Lung Hsu

doi:10.1109/ASPDAC.2015.7059059

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

Liang Che Li, Wen Hsuan Hsu, Kuen Jong Lee, Chun Lung Hsu

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

13 引文斯高帕斯（Scopus）

摘要

TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

原文	???core.languages.en_GB???
主出版物標題	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	520-525
頁數	6
ISBN（電子）	9781479977925
DOIs	https://doi.org/10.1109/ASPDAC.2015.7059059
出版狀態	已出版 - 11 3月 2015
事件	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan 持續時間: 19 1月 2015 → 22 1月 2015

出版系列

名字	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
國家/地區	Japan
城市	Chiba
期間	19/01/15 → 22/01/15

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10.1109/ASPDAC.2015.7059059

引用此

Li, L. C., Hsu, W. H., Lee, K. J., & Hsu, C. L. (2015). An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. 於 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (頁 520-525). 文章 7059059 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7059059

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title = "An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST",

abstract = "TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.",

keywords = "3D-IC, Memory BIST, TSV testing",

author = "Li, {Liang Che} and Hsu, {Wen Hsuan} and Lee, {Kuen Jong} and Hsu, {Chun Lung}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 ; Conference date: 19-01-2015 Through 22-01-2015",

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Li, LC, Hsu, WH, Lee, KJ & Hsu, CL 2015, An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. 於 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7059059, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., 頁 520-525, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 19/01/15. https://doi.org/10.1109/ASPDAC.2015.7059059

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. / Li, Liang Che; Hsu, Wen Hsuan; Lee, Kuen Jong 等.
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 520-525 7059059 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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T1 - An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

AU - Li, Liang Che

AU - Hsu, Wen Hsuan

AU - Lee, Kuen Jong

AU - Hsu, Chun Lung

PY - 2015/3/11

Y1 - 2015/3/11

N2 - TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

AB - TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

KW - 3D-IC

KW - Memory BIST

KW - TSV testing

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T3 - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

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PB - Institute of Electrical and Electronics Engineers Inc.

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Li LC, Hsu WH, Lee KJ, Hsu CL. An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. 於 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 520-525. 7059059. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). doi: 10.1109/ASPDAC.2015.7059059

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

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