An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing

Wei Chang; Yu Guang Chen; Po Yeh Huang; Jin Fu Li

doi:10.1109/DFT52944.2021.9568343

An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing

Wei Chang, Yu Guang Chen, Po Yeh Huang, Jin Fu Li

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

4 引文斯高帕斯（Scopus）

摘要

In-memory computing (IMC), which processes data directly in memory arrays through analog signal capture, provides fast and efficient Boolean logic computation. One of such a structure is SRAM-based IMC, which uses the discharge amplitude to realize various Boolean functions. However, the PVT variations as well as aging effects will seriously impact the accuracy of the IMC results. To improve the accuracy and to extend the system lifetime, in this paper we propose a novel 8T CMOS SRAM IMC structure which uses supplemental transistors to tolerance the PBTI effects on NMOS transistors. Experimental results show a significant lifetime extension with the proposed method.

原文	???core.languages.en_GB???
主出版物標題	34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021
編輯	Luigi Dilillo, Luca Cassano, Athanasios Papadimitriou
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781665416092
DOIs	https://doi.org/10.1109/DFT52944.2021.9568343
出版狀態	已出版 - 2021
事件	34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021 - Virtual, Athens, Greece 持續時間: 6 10月 2021 → 8 10月 2021

出版系列

名字	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
卷	2021-October
ISSN（列印）	2576-1501
ISSN（電子）	2765-933X

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021
國家/地區	Greece
城市	Virtual, Athens
期間	6/10/21 → 8/10/21

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10.1109/DFT52944.2021.9568343

引用此

Chang, W., Chen, Y. G., Huang, P. Y., & Li, J. F. (2021). An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. 於 L. Dilillo, L. Cassano, & A. Papadimitriou (編輯), 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; 卷 2021-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT52944.2021.9568343

Chang, Wei ; Chen, Yu Guang ; Huang, Po Yeh 等. / An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021. 編輯 / Luigi Dilillo ; Luca Cassano ; Athanasios Papadimitriou. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

@inproceedings{f4c8727f3936423fa9e058bd03dc4438,

title = "An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing",

abstract = "In-memory computing (IMC), which processes data directly in memory arrays through analog signal capture, provides fast and efficient Boolean logic computation. One of such a structure is SRAM-based IMC, which uses the discharge amplitude to realize various Boolean functions. However, the PVT variations as well as aging effects will seriously impact the accuracy of the IMC results. To improve the accuracy and to extend the system lifetime, in this paper we propose a novel 8T CMOS SRAM IMC structure which uses supplemental transistors to tolerance the PBTI effects on NMOS transistors. Experimental results show a significant lifetime extension with the proposed method.",

keywords = "8T SRAM, In-Memory Computing, PBTI, supplemental transistor",

author = "Wei Chang and Chen, {Yu Guang} and Huang, {Po Yeh} and Li, {Jin Fu}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021 ; Conference date: 06-10-2021 Through 08-10-2021",

year = "2021",

doi = "10.1109/DFT52944.2021.9568343",

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series = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Chang, W, Chen, YG, Huang, PY & Li, JF 2021, An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. 於 L Dilillo, L Cassano & A Papadimitriou (編輯), 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, 卷 2021-October, Institute of Electrical and Electronics Engineers Inc., 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Virtual, Athens, Greece, 6/10/21. https://doi.org/10.1109/DFT52944.2021.9568343

An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. / Chang, Wei; Chen, Yu Guang; Huang, Po Yeh 等.
34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021. 編輯 / Luigi Dilillo; Luca Cassano; Athanasios Papadimitriou. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; 卷 2021-October).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

TY - GEN

T1 - An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing

AU - Chang, Wei

AU - Chen, Yu Guang

AU - Huang, Po Yeh

AU - Li, Jin Fu

PY - 2021

Y1 - 2021

N2 - In-memory computing (IMC), which processes data directly in memory arrays through analog signal capture, provides fast and efficient Boolean logic computation. One of such a structure is SRAM-based IMC, which uses the discharge amplitude to realize various Boolean functions. However, the PVT variations as well as aging effects will seriously impact the accuracy of the IMC results. To improve the accuracy and to extend the system lifetime, in this paper we propose a novel 8T CMOS SRAM IMC structure which uses supplemental transistors to tolerance the PBTI effects on NMOS transistors. Experimental results show a significant lifetime extension with the proposed method.

AB - In-memory computing (IMC), which processes data directly in memory arrays through analog signal capture, provides fast and efficient Boolean logic computation. One of such a structure is SRAM-based IMC, which uses the discharge amplitude to realize various Boolean functions. However, the PVT variations as well as aging effects will seriously impact the accuracy of the IMC results. To improve the accuracy and to extend the system lifetime, in this paper we propose a novel 8T CMOS SRAM IMC structure which uses supplemental transistors to tolerance the PBTI effects on NMOS transistors. Experimental results show a significant lifetime extension with the proposed method.

KW - 8T SRAM

KW - In-Memory Computing

KW - PBTI

KW - supplemental transistor

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T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT

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A2 - Papadimitriou, Athanasios

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021

Y2 - 6 October 2021 through 8 October 2021

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Chang W, Chen YG, Huang PY, Li JF. An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. 於 Dilillo L, Cassano L, Papadimitriou A, 編輯, 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021. Institute of Electrical and Electronics Engineers Inc. 2021. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). doi: 10.1109/DFT52944.2021.9568343

An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing

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