An adaptive low-power control scheme for on-chip network applications

Systems-on-chip (SoC) is evolving toward complex heterogeneous multiprocessors made of many pre-designed cores or IPs with application specific interconnections. Intra-chip interconnects are thus becoming one of the central elements of SoC design and pose conflicting goals in terms of low energy per transmitted bit, guaranteed signal integrity, and ease of design. This paper presents a low-power control policy for on-chip network applications. The proposed scheme uses the dynamic voltage scaling (DVS) approach to deal with low swing signaling and error detection codes for error rate detecting. Simulation results show that the proposed scheme can effectively save the energy consumption with different data links in an on-chip network.