All digital phase-locked loop using active inductor oscillator and novel locking algorithm

Keyphrases

• All-digital Phase-locked Loop (ADPLL) 100%
• Active Inductor 100%
• Operational Frequency 50%
• Core Size 25%
• Power Consumption 25%
• Frequency Locking 25%
• Phase Locking 25%
• CMOS Process 25%
• Small Area 25%
• Jitter Performance 25%
• Peak-to-peak Jitter 25%
• Fast Lock 25%
• Frequency Accuracy 25%
• 0.18-μm CMOS Technology 25%
• Circuit Complexity 25%
• LC Tank 25%
• Signal Quality 25%
• High Signal 25%
• Tunable Inductor 25%

Engineering

• Phase Locked Loop 100%
• Active Inductor 100%
• Oscillator 100%
• Electric Power Utilization 25%
• Signal Quality 25%
• Core Size 25%