All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application

Chih Wei Tsai, Yu Lung Lo, Chia Chen Chang, Han Ying Liu, Wei Bin Yang, Kuo Hsing Cheng

研究成果: 雜誌貢獻期刊論文同行評審

摘要

A synchronous and highly accurate all-digital duty-cycle corrector (ADDCC), which uses simplified dual-loop architecture, is presented in this paper. To explain the operational principle, a detailed circuit description and formula derivation are provided. To verify the proposed design, a chip was fabricated through the 0.18-μm standard complementary metal oxide semiconductor process with a core area of 0.091mm2. The measurement results indicate that the proposed ADDCC can operate between 300 and 600 MHz with an input duty-cycle range of 40-60%, and that the output duty-cycle error is less than 1% with a root-mean-square jitter of 3.86 ps.

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文章編號04CF02
期刊Japanese Journal of Applied Physics
56
發行號4
DOIs
出版狀態已出版 - 4月 2017

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