@inproceedings{6537f18d3b22475e9dd9753b7b33a492,
title = "A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application",
abstract = "This paper presents an all-digital delay-locked loop (ADDLL) with wide operating range for double data rate synchronous dynamic random access memory (DDR SDRAM) application. To avoid the quadrature phase error caused by harmonic lock, the proposed auto-calibrated edge detector (ACED) utilizes novel harmonic lock detection technique and auto-calibration technique to extend the operating range. To verify, the proposed circuit was fabricated using 90-nm standard CMOS process with a 1-V supply voltage. The core area is 0.089 mm2. The measurement result shows the operating range of proposed ADDLL is from 0.1 to 2.7 GHz with peak-to-peak period jitter less than 5 ps. The quadrature output duty-cycle error is less than 1.9%.",
keywords = "all-digital delay-locked loop (ADDLL), double data rate synchronous dynamic random access memory (DDR SDRAM), duty cycle, harmonic lock, stuck lock",
author = "Tsai, {Chih Wei} and Chiu, {Yu Ting} and Tu, {Yo Hao} and Cheng, {Kuo Hsing}",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",
year = "2018",
month = apr,
day = "26",
doi = "10.1109/ISCAS.2018.8350995",
language = "???core.languages.en_GB???",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings",
}